Commit bff0e8ce authored by Benoit Fabrèges's avatar Benoit Fabrèges
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fix md job_d6f2a53a76a2c0ad8f000aa9e995ef68.md

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...@@ -14,7 +14,7 @@ Job_Employer: CentralaSupelec ...@@ -14,7 +14,7 @@ Job_Employer: CentralaSupelec
Expiration_Date: 2021-12-31 Expiration_Date: 2021-12-31
Attachment: job_d6f2a53a76a2c0ad8f000aa9e995ef68_attachment.pdf Attachment: job_d6f2a53a76a2c0ad8f000aa9e995ef68_attachment.pdf
**SKA computing, an HPC challenge** The exascale radio telescope Square Kilometre Array (SKA) [1] will require supercomputers with high technical demands. The Science Data Processor (SDP) pipeline [2] in charge of producing the multidimensional images of the sky will have to execute in realtime a complex algorithm chain with data coming from telescopes at an incredible rate of several Tb/s and limited storage possibilities. The SDP will also have to be as green as possible with an energy budget of only 1 MWatt for 250 Petaflops. **SKA computing, an HPC challenge.** The exascale radio telescope Square Kilometre Array (SKA) [1] will require supercomputers with high technical demands. The Science Data Processor (SDP) pipeline [2] in charge of producing the multidimensional images of the sky will have to execute in realtime a complex algorithm chain with data coming from telescopes at an incredible rate of several Tb/s and limited storage possibilities. The SDP will also have to be as green as possible with an energy budget of only 1 MWatt for 250 Petaflops.
**FPGA as an alternative to GPU.** Aside from the GPU mainstream architecture, alternative accelerators present better power-efficiency and cannot be already aside the road for the final SDP implementation. Among the alternative solutions, FPGA is an hardware architecture offering a unique fine-grain task and data parallelism compared to architectures based on processors like CPU, GPU or Kalray MPPA with a design dedicated to algorithms. However, the usual synthesis flows require hard- ware expertise and long implementation time. One of the promises of the emerging High Level Synthesis (HLS) tools is to make FPGA development accessible by software engineers with hardware implementa- tions generated from software programming languages like C, C++, or OpenCL. Afterwards, the FPGA design can be optimised gradually with the integration of hardware blocks. The dedicated FPGA solutions usually outperform GPU ones using the whole available computing power and avoiding memory congestion. First results obtained by the Astron Team for radioastronomy are already encouraging [3]. **FPGA as an alternative to GPU.** Aside from the GPU mainstream architecture, alternative accelerators present better power-efficiency and cannot be already aside the road for the final SDP implementation. Among the alternative solutions, FPGA is an hardware architecture offering a unique fine-grain task and data parallelism compared to architectures based on processors like CPU, GPU or Kalray MPPA with a design dedicated to algorithms. However, the usual synthesis flows require hard- ware expertise and long implementation time. One of the promises of the emerging High Level Synthesis (HLS) tools is to make FPGA development accessible by software engineers with hardware implementa- tions generated from software programming languages like C, C++, or OpenCL. Afterwards, the FPGA design can be optimised gradually with the integration of hardware blocks. The dedicated FPGA solutions usually outperform GPU ones using the whole available computing power and avoiding memory congestion. First results obtained by the Astron Team for radioastronomy are already encouraging [3].
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**PostDoc Goal.** Exploration of the potential of FPGA acceleration with High Level Synthesis tools will be done through the design of an SDP prototype for NenuFAR [11] ; this very large low-frequency radio telescope located at Nan ̧cay Observatory has been inaugurated in Oct. 2019. It will produce visibility throughput about one hundred times lower than SKA1-LOW and adjustable to the single node prototype capabilities. The FPGA prototype will be designed through Intel FPGA SDK for OpenCL ; The FPGA prototype will be set up at Nanc ̧ay, connected to the correlator output visibility stream, to run in realtime its SDP pipeline. A main interest of this study is to deliver performance feedbacks in time, memory and energy to SimSDP. Indeed evaluation of the performance gain using FPGA inside HPC nodes in this specific use case, will be particulary useful to assess which role FPGA could play in future SKA like HPC projects. **PostDoc Goal.** Exploration of the potential of FPGA acceleration with High Level Synthesis tools will be done through the design of an SDP prototype for NenuFAR [11] ; this very large low-frequency radio telescope located at Nan ̧cay Observatory has been inaugurated in Oct. 2019. It will produce visibility throughput about one hundred times lower than SKA1-LOW and adjustable to the single node prototype capabilities. The FPGA prototype will be designed through Intel FPGA SDK for OpenCL ; The FPGA prototype will be set up at Nanc ̧ay, connected to the correlator output visibility stream, to run in realtime its SDP pipeline. A main interest of this study is to deliver performance feedbacks in time, memory and energy to SimSDP. Indeed evaluation of the performance gain using FPGA inside HPC nodes in this specific use case, will be particulary useful to assess which role FPGA could play in future SKA like HPC projects.
**Candidate Profile.** **Candidate Profile.**
1. PhD in computer science (or signal processing); 1. PhD in computer science (or signal processing);
2. Experience in computing acceleration on FPGA (Intel or Xilinx) or GPU (Cuda/OpenCL); 3. Good background in signal processing; 2. Experience in computing acceleration on FPGA (Intel or Xilinx) or GPU (Cuda/OpenCL);
3. Good background in signal processing;
4. Experience in publishing high quality research papers. 4. Experience in publishing high quality research papers.
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